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10/2009 awu6601 help3 tm band 1 / wcdma / td-scdma 3.4 v / 28.25 dbm linear pa module data sheet - rev 2.0 m45 package 10 pin 3 mm x 3 mm x 1 mm surface mount module figure 1: block diagram features ? hspa compliant ? ingap hbt technology ? low quiescent current with only 2 bias modes ? simpler calibration ? low leakage current in shutdown mode: <1 a ? internal voltage regulator ? integrated daisy chainable directional couplers with cpl in and cpl out ports ? optimized for a 50 ? system ? low profle miniature surface mount package ? rohs compliant package, 260 o c msl-3 wcdma/hspa mode ? high effciency: (r99 waveform) 40 % @ p out = +28.25 dbm 25 % @ p out = +17 dbm low quiescent current: 8 ma td-scdma mode 36 % @ p out = +27 dbm 20 % @ p out = +16 dbm applications ? wireless handsets and data devices for ? wcdma/hspa imt-band ? td-scdma 1.8/2.0 ghz band product description the awu6601 help3 tm pa is a 3rd generation wcdma product for umts handsets. this pa incorporates anadigics help3 tm technology to provide low power consumption without the need for an external voltage regulator. a daisy chainable directional coupler is integrated in the module thus eliminating the need of external couplers. the device is manufactured on an advanced ingap hbt mmic technology offering state-of-the-art reliability, temperature stability, and ruggedness. there are two selectable bias modes that optimize effciency for different output power levels, and a shutdown mode with low leakage current, which increases handset talk and standby time. the self-contained 3 mm x 3 mm x 1 mm surface mount package incorporates matching networks optimized for output power, effciency, and linearity in a 50 ? system. aw u6601 1 2 3 4 5 10 9 8 7 6 v bat t rf in v mode2 (n/c) v mode 1 v en cp l ou t gn d cp l in rf ou t v cc bias control voltage regulation cp l gnd at slug (pad )
2 data sheet - rev 2.0 10/2009 awu6601 figure 2: pinout (x-ray top view) table 1: pin description v bat t rf in v mode2 (n/c) v mode 1 v en 1 2 3 4 5 6 7 8 9 10 cp l ou t gn d cp l in rf ou t v cc 1 2 3 4 5 6 7 8 9 10 pin name description 1 v batt battery voltage 2 rf in rf input 3 v mode2 (n/c) no connection 4 v mode1 mode control voltage 1 5 v en pa enable voltage 6 cpl out coupler output 7 gnd ground 8 cpl in coupler input 9 rf out rf output 10 v cc supply voltage
data sheet - rev 2.0 10/2009 awu6601 3 electrical characteristics table 2: absolute minimum and maximum ratings stresses in excess of the absolute ratings may cause permanent damage. functional operation is not implied under these conditions. exposure to absolute ratings for extended periods of time may adversely affect reliability. table 3: operating ranges the device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defned in the electrical specifcations. notes: (1) for operation at v c c = +3.2 v, p o u t is derated by 0.5 db. parameter min max unit supply voltage (v cc ) 0 +5 v battery voltage (v batt ) 0 +6 v control voltages (v mode1 , v enable ) 0 +3.5 v rf input power (p in ) - +10 dbm storage temperature (t stg ) -40 +150 c parameter min typ max unit comments operating frequency (f) 1920 1880 2010 - - - 1980 1920 2025 mhz umts band 1 td-scdma band td-scdma band supply voltage (v cc ) +3.2 +3.4 +4.2 v p out < +28.25 dbm enable voltage (v enable ) +2.15 0 +2.4 0 +3.1 +0.5 v pa "on" pa "shut down" mode control voltage (v mode1 ) +2.15 0 +2.4 0 +3.1 +0.5 v low bias mode high bias mode rf output power (p out ) r99 wcdma, hpm hspa (mpr=0), hpm r99 wcdma, lpm hspa (mpr=0), lpm 27.75 (1) 26.75 (1) 16.5 (1) 15.5 (1) 28.25 27.25 17 16 28.25 27.25 17 16 dbm 3gpp ts 34.121-1, rel 8 table c.11.1.3, subtest 1 rf output power (p out ), td-scdma td-scdma (hpm) td-scdma (lpm) 26.5 15.5 27 16.0 27 16.0 dbm 3gpp ts 25.62 section 6.2.1 case temperature (t c ) -30 - +90 c
4 data sheet - rev 2.0 10/2009 awu6601 table 4: electrical specifcations - umts/wcdma mode (t c = +25 c, v cc = +3.4 v, v batt = +3.4 v, v enable = +2.4 v, 50 ? system, r99 waveform) notes: (1) aclr and effciency measured at 1950 mhz. (2) noise measured at 2110 mhz to 2170 mhz. parameter min typ max unit comments p out v mode1 gain 24.5 11.5 26.5 13.5 16.5 db +28.25 dbm +17 dbm 0 v 2.4 v aclr1 at 5 mhz offset - - -41 -42 -38 -38 dbc +28.25 dbm +17 dbm 0 v 2.4 v aclr2 at 10 mhz offset - - -55 -55 -48 -48 dbc +28.25 dbm +17 dbm 0 v 2.4 v power-added efficiency 36 21 40 25 - - % +28.25 dbm +17 dbm 0 v 2.4 v 4lhvfhqwuuhqw,ft low bias mode - 8 12 ma v mode1 = +2.4 v mode control current - 0.3 0.6 ma through v mode pin, v mode1 = +2.4 v enable current - 0.3 0.6 ma through v enable pin batt current - 3.0 5 ma through v batt pin, v mode1 = +2.4 v leakage current - <1 5 a v batt = +4.2 v, v cc = +4.2 v, v enable = 0 v, v mode1 = 0 v 1rlvhlq5hfhlh%dqg - -137 -135 dbm/hz p out < +28.25 dbm, v mode1 = 0v - -143 -138 dbm/hz p out < 17 dbm, v mode1 = +2.4 v harmonics 2fo 3fo, 4fo - - -42 -50 -35 -35 dbc p out < +28.25 dbm input impedance - - 2:1 vswr coupling factor - - db luhfwllw - 20 - db 6sulrv2wsw/hho doovsulrvrwswv - - -70 dbc p out < +28.25 dbm in-band load vswr < 5:1 out-of-band load vswr < 10:1 ssolhvrhudoorshudwlq conditions load mismatch stress with no permanent degradation or failure 8:1 - - vswr ssolhvrhuioorshudwlqudqh
data sheet - rev 2.0 10/2009 awu6601 5 table 5: electrical specifcations - td-scdma mode (t c = +25 c, v cc = +3.4 v, v batt = +3.4 v, v enable = +2.4 v, 50 ? system) parameter min typ max unit comments p out v mode1 gain 24 11.5 27 13.5 - - db +27 dbm +16 dbm 0 v 2.4 v aclr1 at 1.6 mhz offset - - -42 -42 -38 -38 dbc +27 dbm +16 dbm 0 v 2.4 v aclr2 at 3.2 mhz offset - - -55 -55 -48 -48 dbc +27 dbm +16 dbm 0 v 2.4 v power-added efficiency (without dc/dc converter) 33 18 36 20 - - % +27 dbm +16 dbm 0 v 2.4 v quiescent current (icq) low bias mode - 8 12 ma v mode1 = +2.4 v mode control current - 0.3 0.6 ma through v mode pin, v mode1 = +2.4 v enable current - 0.3 0.6 ma through v enable pin, v en = +2.4 v batt current - 3.0 5 ma through v batt pin, v mode1 = +2.4 v leakage current - <1 5 a v batt = +4.3 v, v cc = +4.3 v, v enable = 0 v, v mode1 = 0 v harmonics 2fo 3fo, 4fo - - - - -35 -35 dbc p out < +27 dbm input impedance - - 2:1 vswr load mismatch stress with no permanent degradation or failure 8:1 - - vswr applies over full operating range
6 data sheet - rev 2.0 10/2009 awu6601 application information to ensure proper performance, refer to all related application notes on the anadigics web site: http://www.anadigics.com shutdown mode the power amplifer may be placed in a shutdown mode by applying logic low levels (see operating ranges table) to the v enable and v mode1 voltages. bias modes the power amplifer may be placed in either a low bias mode or a high bias mode by applying the appropriate logic level (see operating ranges table) to v mode1 . the bias control table lists the recommended modes of operation for various applications. v mode2 is not necessary for this pa. two operating modes are available to optimize current consumption. high bias/high power operating mode is for p out levels > 16 dbm. at around 17 dbm output power, the pa should be mode switched to medium/low power mode for lowest quiescent current consumption. table 6: bias control (wcdma/umts) table 7: bias control (td-scdma) application p out levels bias mode v enable v mode1 v cc v b at t umts - high power (high bias mode) > +16 dbm high +2.4 v 0 v 3.2 - 4.2 v > 3.2 v umts - med/low power (low bias mode) < +17 dbm low +2.4 v +2.4 v 3.2 - 4.2 v > 3.2 v optional lower v cc in low power mode < +7 dbm low +2.4 v +2.4 v 1.5 v > 3.2 v shutdown - shutdown 0 v 0 v 3.2 - 4.2 v > 3.2 v application p out levels bias mode v enable v mode1 v cc v b at t td-scdma - high power (high bias mode) > +15 dbm high +2.4 v 0 v 3.2 - 4.2 v > 3.2 v td-scdma - med/low power (low bias mode) < +16 dbm low +2.4 v +2.4 v 3.2 - 4.2 v > 3.2 v shutdown - shutdown 0 v 0 v 3.2 - 4.2 v > 3.2 v
data sheet - rev 2.0 10/2009 awu6601 7 characterization data (wcdma rel 99, v cc = 3.4 v, v en = 2.4 v, t = 25 8c) 0 5 10 15 20 25 30 -10 -5 0 5 10 15 20 25 30 pout (dbm) gain (db) 1920mhz 1950mhz 1980mhz 0 50 100 150 200 250 300 350 400 450 500 550 -10 -5 0 5 10 15 20 25 30 pout (dbm) current (ma) 1920mhz 1950mhz 1980mhz -70 -65 -60 -55 -50 -45 -40 -35 -30 -10 -5 0 5 10 15 20 25 30 pout (dbm) aclr1 (dbc) 1920mhz 1950mhz 1980mhz -80 -75 -70 -65 -60 -55 -50 -45 -40 -10 -5 0 5 10 15 20 25 30 pout (dbm) aclr2 (dbc) 1920mhz 1950mhz 1980mhz 0 5 10 15 20 25 30 35 40 45 -10 -5 0 5 10 15 20 25 30 pout (dbm) pae (%) 1920mhz 1950mhz 1980mhz figure 3: gain vs output power figure 4: current vs output power figure 5: aclr1 (5 mhz offset) vs output power figure 6: aclr2 (10 mhz offset) vs output figure 7: effciency vs output power
8 data sheet - rev 2.0 10/2009 awu6601 characterization data (hspa, rel 8, v cc = 3.4 v, v en = 2.4 v, t = 25 8c) figure 8: gain vs output power figure 9: current vs output power figure 10: aclr1 (5mhz offset) vs output power figure 11: aclr2 (10mhz offset) vs output figure 12: effciency vs output power 0 5 10 15 20 25 30 -10 -5 0 5 10 15 20 25 30 pout (dbm) gain (db) 1920mhz 1950mhz 1980mhz 0 50 100 150 200 250 300 350 400 450 500 550 -10 -5 0 5 10 15 20 25 30 pout (dbm) current (ma) 1920mhz 1950mhz 1980mhz -65 -60 -55 -50 -45 -40 -35 -30 -10 -5 0 5 10 15 20 25 30 pout (dbm) aclr1 (dbc) 1920mhz 1950mhz 1980mhz -80 -75 -70 -65 -60 -55 -50 -45 -40 -10 -5 0 5 10 15 20 25 30 pout (dbm) aclr2 (dbc) 1920mhz 1950mhz 1980mhz 0 5 10 15 20 25 30 35 40 -10 -5 0 5 10 15 20 25 30 pout (dbm) pae (%) 1920mhz 1950mhz 1980mhz
data sheet - rev 2.0 10/2009 awu6601 9 figure 13: evaluation board schematic figure 14: evaluation board layout gnd gnd cplout c4 c5 vbatt vcc c2 c3 c6 c1 ven rfin vmode1 rfout cplin gnd gnd vmode2 c3 2.2 f ceramic rf in 1 6 7 10 8 5 4 3 v batt v mode1 rf out rf in gnd v cc v en cpl out v cc c1 33 pf v batt v mode 1 v en cpl in 2 9 v mode2 (n/c) c6 2.2 f c2 0.1 f gnd at slug cpl in c4 68 pf cpl out rf out c5 0.01 f
10 data sheet - rev 2.0 10/2009 awu6601 help3 the awu6601 power amplifer module is based on anadigics proprietary help3? technology. the pa is designed to operate up to 17 dbm in the low power mode, thus eliminating the need for three gain state, while still maintaining low quiescent current and high effciency in low and medium power levels. the pa can still be operated as 3 gain state device if the customer chooses to. the directional daisy chainable coupler is integrated within the pa module, therefore there is no need for external couplers. the awu6601 has an integrated voltage regulator, which eliminates the need for an external constant voltage source. the pa is turn on/off is controlled by v en pin. a single v mode control logic (v mode1 ) is needed to operate this device. the dg09 power distribution (fg 15) highlights the need to improve the current consumption in low and medium power level. the awu6601 is designed to operate up to 17 dbm in the low power mode with very low quiescent current. current consumption for awu6601 is also plotted in the fgure 5. 31. 5 ma a ve ra ge c u rre nt o ve r dg 09 p ro file 0. 000 0. 010 0. 020 0. 030 0. 040 0. 050 0. 060 0. 070 0. 080 0. 090 0. 100 0. 110 0. 120 0. 130 0. 140 0. 150 -6 0- 50 -4 0- 30 -2 0- 10 01 02 03 0 an te nna p ow er ( db m) dg 09 pd f 0 50 100 150 200 250 300 350 400 450 500 aw u 6601 cu rre nt ( ma ) dg 09 p df aw u 6601 (m a) figure 15: pdf and current figure 16: typical application circuit awu6601 requires only two calibration sweeps for system calibration, thus saving calibration time. figure 16 shows one application example on mobile board. c1 and c2 are rf bypass caps and should be placed nearby pin 1 and pin 10. bypass caps c9 and c5 may not be needed. also a t matching topology is recommended at pa rf in and rf out ports to provide matching between input tx filter and duplexer / isolator. v bat t rf in v mo de 2 (n /c ) v mo de 1 v en rf ou t cp l in cp l ou t gn d v cc c1 c2 c6 v bat t c4 c1 0 rf ou t c7 c8 tx fi l te r pa _r 1 pa _r 0 pa _0 n c9 c5 bb g nd a t s l ug l2 (n /c ) l1 rf in 50 gn d gn d gn d gn d gn d gn d gn d gn d to de te ct or du pl exer
data sheet - rev 2.0 10/2009 awu6601 11 figure 17: m45 package outline - 10 pin 3 mm x 3 mm x 1 mm surface mount module figure 18: branding specifcation - m45 package package outline 6601r llllnn yy wwc c pin 1 identifier pa rt number date co de y y=y ear ; ww=w ork week co untr y co de (c c) l ot number
12 data sheet - rev 2.0 10/2009 awu6601 figure 19: recommended pcb layout information pcb and stencil design guideline
data sheet - rev 2.0 10/2009 awu6601 13 component packaging figure 20: tape & reel packaging table 8: tape & reel dimensions pin 1 package type tape width pocket pitch reel capacity max reel dia 3 mm x 3 mm x 1 mm 12 mm 4 mm 2500 7"
warning anadigics products are not intended for use in life support appliances, devices or systems. use of an anadigics product in any such application without written consent is prohibited. important notice anadigics, inc. 141 mount bethel road warren, new jersey 07059, u.s.a. tel: +1 (908) 668-5000 fax: +1 (908) 668-5132 url: http://www.anadigics.com e-mail: mktg@anadigics.com anadigics, inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. the product specifcations contained in advanced product information sheets and preliminary data sheets are subject to change prior to a products formal introduction. information in data sheets have been carefully checked and are assumed to be reliable; however, anadigics assumes no responsibilities for inaccuracies. anadigics strongly urges customers to verify that the information they are using is current before placing orders. data sheet - rev 2.0 10/2009 14 awu6601 ordering information order number temperature range package description component packaging awu6601rm45q7 -30 o c to +90 o c rohs compliant 10 pin 3 mm x 3 mm x 1 mm surface mount module tape and reel, 2500 pieces per reel AWU6601RM45P9 -30 o c to +90 o c rohs compliant 10 pin 3 mm x 3 mm x 1 mm surface mount module partial tape and reel

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